74-sereis
Showing 1–20 of 50 results
7406 (Hex Inverted Buffers with Open-Collector Outputs)
74LS06 is a Hex Inverted Buffers with Open-Collector Outputs – In 14-DIP Package.
6.50EGP
7411 ( Triple 3-input AND gate)
datasheet : https://www.alldatasheet.com/datasheet-pdf/pdf/125557/ETC1/7411.html
74125N (Quad 3-State Buffer)
74LS125N contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the ...
7.00EGP
7414 (Hex Inverting Schmitt Trigger)
The 74HC14 provides six inverting buffers with Schmitt-trigger action. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
6.00EGP
74147 (10-to-4 Line Priority Encoder)
74HC147 provide the 10-line to 4-line priority encoding function by use of the implied decimal “zero”. The “zero” is encoded when all nine data inputs are HIGH, forcing ...
7.50EGP
74153 (Dual 4-Input to 1-Line Multiplexer)
74153 “Dual 4-Input to 1-Line Multiplexer” in DIP package
6.00EGP
74154 (4-to-16 Decoder/Demultiplexer)
Made in japan The 74HC154 decoders accept four active HIGH binary address inputs and provide 16 mutually-exclusive active LOW outputs. The two-input enable gate can ...
20.00EGP
74164 SMD (8-Bit Parallel-Out Serial Shift Registers)
74164 (8-Bit Parallel-Out Serial Shift Registers)
7.00EGP
74165 (8-Bit Parallel-in/Serial out Shift Register)
The 74HC165 are 8-bit parallel-load or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage. When the parallel load ...
6.00EGP
74174N (Hex D Flip-Flop with Reset)
The 74HC174 are hex positive edge -triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR ...
6.00EGP